1. Technical Field
The present invention relates to edge-missing detector structures and, more particularly, to an edge-missing detector structure for use in a phase-locked loop (PLL).
2. Description of Related Art
A phase-locked loop is a circuit structure used extensively in a variety of communication-related devices such as clock/frequency generators, wireless receivers, and telecommunication equipment. With the advancement of technology, phase-locked loops have found applications in systems beyond the field of communication devices. For example, phase-locked loops are now also used in data recovery circuits, frequency synthesizers, and so on.
FIG. 1 is a circuit diagram of a conventional phase-locked loop 100. FIG. 2 is a graph showing characteristic curves of a conventional phase frequency detector 10 and an ideal phase detector. FIG. 3 is a graph showing the comparison of acquisition time between ideal phase detector and conventional phase frequency detector 10 in conventional phase-locked loop 100.
As shown in FIG. 1, the conventional phase-locked loop 100 includes the phase frequency detector 10, a charge pump 20, a loop filter 30, a voltage control oscillator 40, and a frequency divider 50. The phase frequency detector 10 is configured for detecting a phase difference between a first reference frequency EXT generated by a quartz oscillator and a first clock frequency INT obtained by dividing an oscillation frequency Fvco with a divisor signal N. The phase difference detected is then converted by the charge pump 20 into a corresponding current for output.
Referring to FIG. 2, an ideal phase detector has an average output current Iout which is linearly proportional to the phase difference of input signals. In practice, however, the ideal phase detector has never been realized. Therefore, in place of the ideal phase detector, the phase frequency detector 10 is generally used in the phase-locked loop 100. Nevertheless, the phase frequency detector 10 only maintains linear output within an interval of 2π and then, on a cycle of 2π, repeatedly outputs an average output current Iout having a fixed proportion.
Now that the phase frequency detector 10 only maintains linear output when the phase difference is within 2π, if the phase difference between input signals of the phase-locked loop 100 is greater than 2π, the phase frequency detector 10 cannot determine the phase difference accurately, and thus an average output current corresponding to the actual phase difference cannot be generated, thereby causing cycle slip to the phase-locked loop 100; furthermore, as shown in FIG. 3, the phase-locked loop 100 using the phase frequency detector 10 must take a longer acquisition time to lock the accurate phase than when an ideal linear phase detector were used.
As mentioned earlier, the ideal linear phase detector cannot be actually made. Therefore, U.S. Pat. No. 7,003,065 B2 discloses a phase-locked loop cycle slip detection circuit that includes: a phase detector having a first input circuit, a second input circuit, and a reset circuit; and a cycle slip detector for generating a slip indication signal.
According to disclosure of the above-cited US patent, the cycle slip detector controls the output current value of the phase detector when the phase difference of input signals is greater than 2π, thereby reducing errors resulting from cycle slip of the phase-locked loop. However, the subject matter of the aforesaid US patent can only determine whether or not the phase difference of the input signals is greater than 2π, but cannot accurately determine how many times as great the phase difference of the input signals is as 2π. Hence, the function of the ideal linear phase detector is yet to be attained.